Error correction bypass for erased pages

ABSTRACT

A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.

BACKGROUND

Solid-state memory, such as flash, is currently in use in solid-state drives (SSD) to augment or replace conventional hard disk drives (HDD), writable CD (compact disk) or writable DVD (digital versatile disk) drives, collectively known as spinning media, and tape drives, for storage of large amounts of data. Flash and other solid-state memories have characteristics that differ from spinning media. This is especially noticeable regarding erasure characteristics. Yet, many solid-state drives are designed to conform to hard disk drive standards for compatibility reasons, which makes it difficult to provide enhanced features or take advantage of unique aspects of flash and other solid-state memory.

It is within this context that the embodiments arise.

SUMMARY

In some embodiments a method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.

In some embodiments, a storage cluster with erasure detection is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of user data. The storage cluster includes a plurality of storage units, each of the plurality of storage units having storage memory and each of the plurality of storage units is configured to store user data as directed by the plurality of storage nodes. Each of the plurality of storage units is configured to establish a connection, via a network, to at least one of the plurality of storage nodes, each of the plurality of storage units configured to detect if there is an erased page in the storage memory, and to identify the erased page, to the at least one of the plurality of storage nodes.

In some embodiments, a storage cluster with page erasure detection is provided. The storage cluster includes a plurality of storage units, each of the plurality of storage units having a plurality of pages of storage memory. The storage cluster includes a plurality of storage nodes, coupled together as a storage cluster, each of the plurality of storage nodes configured to direct storage of user data in the plurality of storage units. Each of the plurality of storage units having, as an output to one or more of the plurality of storage nodes, an indicator of erase state of at least one of the plurality of pages of storage memory and each of the plurality of storage units configured to establish a connection, via a network, to at least one of the plurality of storage nodes, configured to determine the erase state of the at least one of the plurality of pages, and configured to communicate the erase state of the at least one of the plurality of pages to the at least one of the plurality of storage nodes via the indicator.

Other aspects and advantages of the embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the described embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The described embodiments and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings. These drawings in no way limit any changes in form and detail that may be made to the described embodiments by one skilled in the art without departing from the spirit and scope of the described embodiments.

FIG. 1 is a perspective view of a storage cluster with multiple storage nodes and internal storage coupled to each storage node to provide network attached storage, in accordance with some embodiments.

FIG. 2 is a block diagram showing an interconnect switch coupling multiple storage nodes in accordance with some embodiments.

FIG. 3 is a multiple level block diagram, showing contents of a storage node and contents of one of the non-volatile solid state storage units in accordance with some embodiments.

FIG. 4 is a block diagram of a storage unit with an erase detector that outputs an indicator of erase state of storage memory of the storage unit to a storage node in accordance with some embodiments.

FIG. 5 is a block diagram showing raw page data, error correction code logic and corrected data in accordance with some embodiments.

FIG. 6 is a block diagram showing the location of the erase detector of FIG. 4 between the raw page data and error correction code logic of FIG. 5 , in an embodiment of a storage unit in accordance with some embodiments.

FIG. 7A-1 through 7A-3 illustrate examples of erase detection in accordance with some embodiments.

FIG. 7B is a block diagram of erase detection logic, a control module and a vector register in an embodiment of the erase detector of FIG. 4 , which may use the erase detection of FIG. 7A in accordance with some embodiments.

FIG. 8 depicts pages in a block of flash memory, with a boundary between valid pages and erased pages as determined by the erase detector of FIG. 4 in accordance with some embodiments.

FIG. 9 is a flow diagram of a method for erasure detection in a storage cluster, which can be practiced by embodiments shown in FIGS. 1-8 .

FIG. 10 is an illustration showing an exemplary computing device which may implement the embodiments described herein.

DETAILED DESCRIPTION

A storage cluster with storage nodes, storage units and hardware assisted erase block state detection is herein described. Each of one or more storage units in the storage cluster has erase detection logic and an indicator from storage unit to storage node that informs the storage node of erase state of pages in storage memory of the storage unit. Aspects of the storage cluster, storage nodes in storage units are described with reference to FIGS. 1-3 . Aspects of the erase detection are described with reference to FIGS. 4-9 .

The embodiments below describe a storage cluster that stores user data, such as user data originating from one or more user or client systems or other sources external to the storage cluster. The storage cluster distributes user data across storage nodes housed within a chassis, using erasure coding and redundant copies of metadata. Erasure coding refers to a method of data protection or reconstruction in which data is stored across a set of different locations, such as disks, storage nodes or geographic locations. Flash memory is one type of solid-state memory that may be integrated with the embodiments, although the embodiments may be extended to other types of solid-state memory or other storage medium, including non-solid state memory. Control of storage locations and workloads are distributed across the storage locations in a clustered peer-to-peer system. Tasks such as mediating communications between the various storage nodes, detecting when a storage node has become unavailable, and balancing I/Os (inputs and outputs) across the various storage nodes, are all handled on a distributed basis. Data is laid out or distributed across multiple storage nodes in data fragments or stripes that support data recovery in some embodiments. Ownership of data can be reassigned within a cluster, independent of input and output patterns. This architecture described in more detail below allows a storage node in the cluster to fail, with the system remaining operational, since the data can be reconstructed from other storage nodes and thus remain available for input and output operations. In various embodiments, a storage node may be referred to as a cluster node, a blade, or a server.

The storage cluster is contained within a chassis, i.e., an enclosure housing one or more storage nodes. A mechanism to provide power to each storage node, such as a power distribution bus, and a communication mechanism, such as a communication bus that enables communication between the storage nodes are included within the chassis. The storage cluster can run as an independent system in one location according to some embodiments. In one embodiment, a chassis contains at least two instances of both the power distribution and the communication bus which may be enabled or disabled independently. The internal communication bus may be an Ethernet bus, however, other technologies such as Peripheral Component Interconnect (PCI) Express, InfiniBand, and others, are equally suitable. The chassis provides a port for an external communication bus for enabling communication between multiple chassis, directly or through a switch, and with client systems. The external communication may use a technology such as Ethernet, InfiniBand, Fibre Channel, etc. In some embodiments, the external communication bus uses different communication bus technologies for inter-chassis and client communication. If a switch is deployed within or between chassis, the switch may act as a translation between multiple protocols or technologies. When multiple chassis are connected to define a storage cluster, the storage cluster may be accessed by a client using either proprietary interfaces or standard interfaces such as network file system (NFS), common internet file system (CIFS), small computer system interface (SCSI) or hypertext transfer protocol (HTTP). Translation from the client protocol may occur at the switch, chassis external communication bus or within each storage node.

Each storage node may be one or more storage servers and each storage server is connected to one or more non-volatile solid state memory units, which may be referred to as storage units. One embodiment includes a single storage server in each storage node and between one to eight non-volatile solid state memory units, however this one example is not meant to be limiting. The storage server may include a processor, dynamic random access memory (DRAM) and interfaces for the internal communication bus and power distribution for each of the power buses. Inside the storage node, the interfaces and storage unit share a communication bus, e.g., PCI Express, in some embodiments. The non-volatile solid state memory units may directly access the internal communication bus interface through a storage node communication bus, or request the storage node to access the bus interface. The non-volatile solid state memory unit contains an embedded central processing unit (CPU), solid state storage controller, and a quantity of solid state mass storage, e.g., between 2-32 terabytes (TB) in some embodiments. An embedded volatile storage medium, such as DRAM, and an energy reserve apparatus are included in the non-volatile solid state memory unit. In some embodiments, the energy reserve apparatus is a capacitor, super-capacitor, or battery that enables transferring a subset of DRAM contents to a stable storage medium in the case of power loss. In some embodiments, the non-volatile solid state memory unit is constructed with a storage class memory, such as phase change or magnetoresistive random access memory (MRAM) that substitutes for DRAM and enables a reduced power hold-up apparatus.

One of many features of the storage nodes and non-volatile solid state storage is the ability to proactively rebuild data in a storage cluster. The storage nodes and non-volatile solid state storage can determine when a storage node or non-volatile solid state storage in the storage cluster is unreachable, independent of whether there is an attempt to read data involving that storage node or non-volatile solid state storage. The storage nodes and non-volatile solid state storage then cooperate to recover and rebuild the data in at least partially new locations. This constitutes a proactive rebuild, in that the system rebuilds data without waiting until the data is needed for a read access initiated from a client system employing the storage cluster. These and further details of the storage memory and operation thereof are discussed below.

FIG. 1 is a perspective view of a storage cluster 160, with multiple storage nodes 150 and internal solid-state memory coupled to each storage node to provide network attached storage or storage area network, in accordance with some embodiments. A network attached storage, storage area network, or a storage cluster, or other storage memory, could include one or more storage clusters 160, each having one or more storage nodes 150, in a flexible and reconfigurable arrangement of both the physical components and the amount of storage memory provided thereby. The storage cluster 160 is designed to fit in a rack, and one or more racks can be set up and populated as desired for the storage memory. The storage cluster 160 has a chassis 138 having multiple slots 142. It should be appreciated that chassis 138 may be referred to as a housing, enclosure, or rack unit. In one embodiment, the chassis 138 has fourteen slots 142, although other numbers of slots are readily devised. For example, some embodiments have four slots, eight slots, sixteen slots, thirty-two slots, or other suitable number of slots. Each slot 142 can accommodate one storage node 150 in some embodiments. Chassis 138 includes flaps 148 that can be utilized to mount the chassis 138 on a rack. Fans 144 provide air circulation for cooling of the storage nodes 150 and components thereof, although other cooling components could be used, or an embodiment could be devised without cooling components. A switch fabric 146 couples storage nodes 150 within chassis 138 together and to a network for communication to the memory. In an embodiment depicted in FIG. 1 , the slots 142 to the left of the switch fabric 146 and fans 144 are shown occupied by storage nodes 150, while the slots 142 to the right of the switch fabric 146 and fans 144 are empty and available for insertion of storage node 150 for illustrative purposes. This configuration is one example, and one or more storage nodes 150 could occupy the slots 142 in various further arrangements. The storage node arrangements need not be sequential or adjacent in some embodiments. Storage nodes 150 are hot pluggable, meaning that a storage node 150 can be inserted into a slot 142 in the chassis 138, or removed from a slot 142, without stopping or powering down the system. Upon insertion or removal of storage node 150 from slot 142, the system automatically reconfigures in order to recognize and adapt to the change. Reconfiguration, in some embodiments, includes restoring redundancy and/or rebalancing data or load.

Each storage node 150 can have multiple components. In the embodiment shown here, the storage node 150 includes a printed circuit board 158 populated by a CPU 156, i.e., processor, a memory 154 coupled to the CPU 156, and a non-volatile solid state storage 152 coupled to the CPU 156, although other mountings and/or components could be used in further embodiments. The memory 154 has instructions which are executed by the CPU 156 and/or data operated on by the CPU 156. As further explained below, the non-volatile solid state storage 152 includes flash or, in further embodiments, other types of solid-state memory.

Referring to FIG. 1 , storage cluster 160 is scalable, meaning that storage capacity with non-uniform storage sizes is readily added, as described above. One or more storage nodes 150 can be plugged into or removed from each chassis and the storage cluster self-configures in some embodiments. Plug-in storage nodes 150, whether installed in a chassis as delivered or later added, can have different sizes. For example, in one embodiment a storage node 150 can have any multiple of 4 TB, e.g., 8 TB, 12 TB, 16 TB, 32 TB, etc. In further embodiments, a storage node 150 could have any multiple of other storage amounts or capacities. Storage capacity of each storage node 150 is broadcast, and influences decisions of how to stripe the data. For maximum storage efficiency, an embodiment can self-configure as wide as possible in the stripe, subject to a predetermined requirement of continued operation with loss of up to one, or up to two, non-volatile solid state storage units 152 or storage nodes 150 within the chassis.

FIG. 2 is a block diagram showing a communications interconnect 170 and power distribution bus 172 coupling multiple storage nodes 150. Referring back to FIG. 1 , the communications interconnect 170 can be included in or implemented with the switch fabric 146 in some embodiments. Where multiple storage clusters 160 occupy a rack, the communications interconnect 170 can be included in or implemented with a top of rack switch, in some embodiments. As illustrated in FIG. 2 , storage cluster 160 is enclosed within a single chassis 138. External port 176 is coupled to storage nodes 150 through communications interconnect 170, while external port 174 is coupled directly to a storage node. External power port 178 is coupled to power distribution bus 172. Storage nodes 150 may include varying amounts and differing capacities of non-volatile solid state storage 152 as described with reference to FIG. 1 . In addition, one or more storage nodes 150 may be a compute only storage node as illustrated in FIG. 2 . Authorities 168 are implemented on the non-volatile solid state storages 152, for example as lists or other data structures stored in memory. In some embodiments the authorities are stored within the non-volatile solid state storage 152 and supported by software executing on a controller or other processor of the non-volatile solid state storage 152. In a further embodiment, authorities 168 are implemented on the storage nodes 150, for example as lists or other data structures stored in the memory 154 and supported by software executing on the CPU 156 of the storage node 150. Authorities 168 control how and where data is stored in the non-volatile solid state storages 152 in some embodiments. This control assists in determining which type of erasure coding scheme is applied to the data, and which storage nodes 150 have which portions of the data. Each authority 168 may be assigned to a non-volatile solid state storage 152. Each authority may control a range of inode numbers, segment numbers, or other data identifiers which are assigned to data by a file system, by the storage nodes 150, or by the non-volatile solid state storage 152, in various embodiments.

Every piece of data, and every piece of metadata, has redundancy in the system in some embodiments. In addition, every piece of data and every piece of metadata has an owner, which may be referred to as an authority. If that authority is unreachable, for example through failure of a storage node, there is a plan of succession for how to find that data or that metadata. In various embodiments, there are redundant copies of authorities 168. Authorities 168 have a relationship to storage nodes 150 and non-volatile solid state storage 152 in some embodiments. Each authority 168, covering a range of data segment numbers or other identifiers of the data, may be assigned to a specific non-volatile solid state storage 152. In some embodiments the authorities 168 for all of such ranges are distributed over the non-volatile solid state storages 152 of a storage cluster. Each storage node 150 has a network port that provides access to the non-volatile solid state storage(s) 152 of that storage node 150. Data can be stored in a segment, which is associated with a segment number and that segment number is an indirection for a configuration of a RAID (redundant array of independent disks) stripe in some embodiments. The assignment and use of the authorities 168 thus establishes an indirection to data. Indirection may be referred to as the ability to reference data indirectly, in this case via an authority 168, in accordance with some embodiments. A segment identifies a set of non-volatile solid state storage 152 and a local identifier into the set of non-volatile solid state storage 152 that may contain data. In some embodiments, the local identifier is an offset into the device and may be reused sequentially by multiple segments. In other embodiments the local identifier is unique for a specific segment and never reused. The offsets in the non-volatile solid state storage 152 are applied to locating data for writing to or reading from the non-volatile solid state storage 152 (in the form of a RAID stripe). Data is striped across multiple units of non-volatile solid state storage 152, which may include or be different from the non-volatile solid state storage 152 having the authority 168 for a particular data segment.

If there is a change in where a particular segment of data is located, e.g., during a data move or a data reconstruction, the authority 168 for that data segment should be consulted, at that non-volatile solid state storage 152 or storage node 150 having that authority 168. In order to locate a particular piece of data, embodiments calculate a hash value for a data segment or apply an inode number or a data segment number. The output of this operation points to a non-volatile solid state storage 152 having the authority 168 for that particular piece of data. In some embodiments there are two stages to this operation. The first stage maps an entity identifier (ID), e.g., a segment number, inode number, or directory number to an authority identifier. This mapping may include a calculation such as a hash or a bit mask. The second stage is mapping the authority identifier to a particular non-volatile solid state storage 152, which may be done through an explicit mapping. The operation is repeatable, so that when the calculation is performed, the result of the calculation repeatably and reliably points to a particular non-volatile solid state storage 152 having that authority 168. The operation may include the set of reachable storage nodes as input. If the set of reachable non-volatile solid state storage units changes the optimal set changes. In some embodiments, the persisted value is the current assignment (which is always true) and the calculated value is the target assignment the cluster will attempt to reconfigure towards. This calculation may be used to determine the optimal non-volatile solid state storage 152 for an authority in the presence of a set of non-volatile solid state storage 152 that are reachable and constitute the same cluster. The calculation also determines an ordered set of peer non-volatile solid state storage 152 that will also record the authority to non-volatile solid state storage mapping so that the authority may be determined even if the assigned non-volatile solid state storage is unreachable. A duplicate or substitute authority 168 may be consulted if a specific authority 168 is unavailable in some embodiments.

With reference to FIGS. 1 and 2 , two of the many tasks of the CPU 156 on a storage node 150 are to break up write data, and reassemble read data. When the system has determined that data is to be written, the authority 168 for that data is located as above. When the segment ID for data is already determined the request to write is forwarded to the non-volatile solid state storage 152 currently determined to be the host of the authority 168 determined from the segment. The host CPU 156 of the storage node 150, on which the non-volatile solid state storage 152 and corresponding authority 168 reside, then breaks up or shards the data and transmits the data out to various non-volatile solid state storage 152. The transmitted data is written as a data stripe in accordance with an erasure coding scheme. In some embodiments, data is requested to be pulled, and in other embodiments, data is pushed. In reverse, when data is read, the authority 168 for the segment ID containing the data is located as described above. The host CPU 156 of the storage node 150 on which the non-volatile solid state storage 152 and corresponding authority 168 reside requests the data from the non-volatile solid state storage and corresponding storage nodes pointed to by the authority. In some embodiments the data is read from flash storage as a data stripe. The host CPU 156 of storage node 150 then reassembles the read data, correcting any errors (if present) according to the appropriate erasure coding scheme, and forwards the reassembled data to the network. In further embodiments, some or all of these tasks can be handled in the non-volatile solid state storage 152. In some embodiments, the segment host requests the data be sent to storage node 150 by requesting pages from storage and then sending the data to the storage node making the original request.

In some systems, for example in UNIX-style file systems, data is handled with an index node or inode, which specifies a data structure that represents an object in a file system. The object could be a file or a directory, for example. Metadata may accompany the object, as attributes such as permission data and a creation timestamp, among other attributes. A segment number could be assigned to all or a portion of such an object in a file system. In other systems, data segments are handled with a segment number assigned elsewhere. For purposes of discussion, the unit of distribution is an entity, and an entity can be a file, a directory or a segment. That is, entities are units of data or metadata stored by a storage system. Entities are grouped into sets called authorities. Each authority has an authority owner, which is a storage node that has the exclusive right to update the entities in the authority. In other words, a storage node contains the authority, and that the authority, in turn, contains entities.

Storage clusters 160, in various embodiments as disclosed herein, can be contrasted with storage arrays in general. The storage nodes 150 are part of a collection that creates the storage cluster 160. Each storage node 150 owns a slice of data and the computing required for providing the data. Multiple storage nodes 150 are required to cooperate to store and retrieve the data. Storage memory or storage devices, as used in storage arrays in general, are less involved with processing and manipulating the data. Storage memory or storage devices in a storage array receive commands to read, write, or erase data. The storage memory or storage devices in a storage array are not aware of a larger system in which they are embedded, or what the data means. Storage memory or storage devices in storage arrays can include various types of storage memory, such as RAM, solid state drives, hard disk drives, etc. The storage units 152 described herein have multiple interfaces active simultaneously and serving multiple purposes. In some embodiments, some of the functionality of a storage node 150 is shifted into a storage unit 152, transforming the storage unit 152 into a combination of storage unit 152 and storage node 150. Placing computing (relative to storage data) into the storage unit 152 places this computing closer to the data itself. The various system embodiments have a hierarchy of storage node layers with different capabilities. By contrast, in a storage array, a controller owns and knows everything about all of the data that the controller manages in a shelf or storage devices. In a storage cluster 160, as described herein, multiple controllers in multiple storage units 152 and/or storage nodes 150 cooperate in various ways (e.g., for erasure coding, data sharding, metadata communication and redundancy, storage capacity expansion or contraction, data recovery, and so on).

FIG. 3 is a multiple level block diagram, showing contents of a storage node 150 and contents of a non-volatile solid state storage 152 of the storage node 150. Data is communicated to and from the storage node 150 by a network interface controller (NIC) 202 in some embodiments. Each storage node 150 has a CPU 156, and one or more non-volatile solid state storage 152, as discussed above. Moving down one level in FIG. 3 , each non-volatile solid state storage 152 has a relatively fast non-volatile solid state memory, such as nonvolatile random access memory (NVRAM) 204, and flash memory 206. In some embodiments, NVRAM 204 may be a component that does not require program/erase cycles (DRAM, MRAM, PCM), and can be a memory that can support being written vastly more often than the memory is read from. Moving down another level in FIG. 3 , the NVRAM 204 is implemented in one embodiment as high speed volatile memory, such as dynamic random access memory (DRAM) 216, backed up by energy reserve 218. Energy reserve 218 provides sufficient electrical power to keep the DRAM 216 powered long enough for contents to be transferred to the flash memory 206 in the event of power failure. In some embodiments, energy reserve 218 is a capacitor, super-capacitor, battery, or other device, that supplies a suitable supply of energy sufficient to enable the transfer of the contents of DRAM 216 to a stable storage medium in the case of power loss. The flash memory 206 is implemented as multiple flash dies 222, which may be referred to as packages of flash dies 222 or an array of flash dies 222. It should be appreciated that the flash dies 222 could be packaged in any number of ways, with a single die per package, multiple dies per package (i.e. multichip packages), in hybrid packages, as bare dies on a printed circuit board or other substrate, as encapsulated dies, etc. In the embodiment shown, the non-volatile solid state storage 152 has a controller 212 or other processor, and an input output (I/O) port 210 coupled to the controller 212. I/O port 210 is coupled to the CPU 156 and/or the network interface controller 202 of the flash storage node 150. Flash input output (I/O) port 220 is coupled to the flash dies 222, and a direct memory access unit (DMA) 214 is coupled to the controller 212, the DRAM 216 and the flash dies 222. In the embodiment shown, the I/O port 210, controller 212, DMA unit 214 and flash I/O port 220 are implemented on a programmable logic device (PLD) 208, e.g., a field programmable gate array (FPGA). In this embodiment, each flash die 222 has pages, organized as sixteen kB (kilobyte) pages 224, and a register 226 through which data can be written to or read from the flash die 222. In further embodiments, other types of solid-state memory are used in place of, or in addition to flash memory illustrated within flash die 222.

FIG. 4 is a block diagram of a storage unit 152 with an erase detector 402 that outputs an indicator 406 of erase state of storage memory 404 of the storage unit 152 to a storage node 150. The erase detector 402 is coupled to the storage memory 404, and can be implemented in hardware, firmware, software executing on a processor (e.g. a processor of the storage unit 152), or combinations thereof. The indicator 406 could take the form of bits, bytes or words crossing the boundary from the storage unit 152 to one or more storage nodes 150. In various embodiments, the information about erased state of storage memory 404 is available full time, or upon request, for example as a result of a function call which returns which page or pages are erased, or whether a page is erased, to the storage node 150. The indicator 406 can be communicated from a storage unit 152 to one or more storage nodes 150 via a network, such as the communications interconnect 170 of FIG. 2 , in some embodiments.

In various embodiments, each storage unit 152 is aware of power up. Upon power up, the storage unit 152 establishes a connection via a network to one or more of the storage nodes 150. Then, the storage unit 152 determines which pages 224 of the storage memory 404 are erased, and which pages 224 of the storage memory are non-erased, i.e., are written pages. This determination could take place as a response to powering up, and could be done before making the connection, in parallel while making the connection, or in response to making the connection. Once the storage unit 152 determines erase state of the pages 224, and when the connection is made and communication is available, the storage unit 152 communicates the erase state of the pages 224 to the storage node(s) 150 via the network, using the indicator 406.

FIG. 5 is a block diagram showing raw page data 502, error correction code logic 504 and corrected data 506. The raw page data 502, which may be accompanied by one or more parity bits, is read from the storage memory 404. Error correction code logic 504 applied to the raw page data 502 produces the corrected data 506. This example is shown for purposes of illustrating where an erase detector 402 could be inserted, located or implemented. Error correction code logic 504 can be implemented in software executing on a processor, a software or hardware-based state machine, or combinatorial logic, or combinations thereof in various embodiments. Further implementations of error correction code logic 504 are readily devised.

FIG. 6 is a block diagram showing the location of the erase detector 402 of FIG. 4 between the raw page data 502 and error correction code logic 504 of FIG. 5 , in an embodiment of a storage unit 152. The error correction code logic 504 is shown producing the corrected data 506 and also shown producing error and status information 606, from the raw page data 502. The erase detector 402 is located upstream of the error correction code logic 504, so as to interface directly with the raw page data 502 prior to the error correction code logic 504. An erase detector output 604, in this embodiment, indicates the raw page data 502 shows erasure, i.e., is erased. In some embodiments, the erase detector 402, error correction code logic 504, and respective interfaces and outputs are included in a programmable logic device 602, and the erase detector output 604 is an output of the programmable logic device 602. This could be the same programmable logic device 208 described above with reference to FIG. 3 , or a differing programmable logic device 602 in a storage unit 152.

In various embodiments, a storage unit 152 bypasses error correction code operations on a page 224 when the storage unit 152 determines that the page 224 is an erased page, i.e., has no written data. This could be implemented by disabling error correction code logic 504, e.g., by not running error correction code software, by halting a state machine or transitioning to a state that does not operate the states associated with performing the error correction code operation, disabling or not enabling hardware logic, or otherwise not performing the error correction code operations. This may free up processing cycles, decrease power consumption, or speed up overall operations or improve operating efficiency by not consuming software or hardware resources that would otherwise be needlessly applied to erased pages. Or, results of the error correction code operations could be ignored, as a form of bypassing.

FIGS. 7A-1 through 7A-3 shows examples of erase detection. These examples are suitable for use in the erase detector 402 of FIGS. 4 and 6 . In a first example, an interface 702 is defined for coupling AND logic 704 to the storage memory 404, in order to receive the raw page data 502. The interface 702 could couple to flash or other solid-state integrated circuits, modules or other arrangements or types of storage memory 404. AND logic 704 could be implemented with logic gates, software or firmware, or combinations thereof. In some embodiments, AND logic 704 is implemented without a processor, e.g., using hardware logic only, such as AND gates or NAND gates. Since the erase state of flash memory is all logical ones, a logical AND combination of bits of a flash page (e.g., the raw page data 502) can detect an erased flash page. It should be appreciated that the embodiments are not limited to an AND gate as other logic gates may implemented within logic block 705 to achieve the functionality described herein in this embodiment.

In a second example in FIG. 7A-2 , the interface 702 is defined for coupling valid codeword logic 706 to the storage memory 404, in order to receive the raw page data 502. The valid codeword logic 706 could compare the raw page data 502 to known codewords according to a specification, and indicate whether any valid codeword is found in the raw page data 502. If no valid codeword is found in the raw page data 502, this indicates the raw page data 502 is erased. Such an operation could be performed using hardware combinatorial logic, or read only memory (ROM) lookup, or in various combinations of software, firmware or hardware. In some embodiments, the valid codeword logic 706 is implemented without a processor.

In a third example in FIG. 7A-3 , the interface 702 is defined for coupling a counter 707 with a threshold value 709 to the storage memory 404, in order to receive the raw page data 502. The counter 707 counts bytes of “FF” (i.e., all ones for the erased state) or other data sizes (e.g., bits, bytes or words) of all erased data. In some embodiments, the counter 707 counts the number of bits that do not match an erased pattern. When the count in these embodiments reaches a threshold value 709 (which could be fixed or programmable), the interface 702 declares that the media is erased. In some embodiments, the counter 707 and threshold value 709 are implemented entirely in hardware logic, without a processor. In some embodiments threshold value 709 is programmable and this programmable value can be changed as needed. As noted above alternative logic combinations or variations may be implemented within logic block 705 as FIG. 7A-3 is one example.

FIG. 7B is a block diagram of erase detection logic 708, a control module 712 and a vector register 710 in an embodiment of the erase detector 402 of FIG. 4 , which may use the erase detection of FIG. 7A. Similar to the examples shown in FIG. 7A, the interface 702 is defined for coupling erase detection logic 708 to the storage memory 404, in order to receive the raw page data 502. Erase detection logic 708 could include the AND logic 704, the valid codeword logic 706, or other logic for detecting erasure. A control module 712 is coupled to the interface 702, the erase detection logic 708, and the vector register 710. The control module 712 could be implemented as a state machine in hardware, or software executing on a processor, or various combinations of software, firmware and hardware (e.g., counters, logic gates). In one embodiment, the control module 712 cycles the interface 702 through reads of the storage memory 404, so that the erase detection logic 708 sees a succession of pages of the storage memory 404, i.e., sees the raw page data 502 of each of the pages. Each time the raw page data 502 of a page from the storage memory 404 is analyzed by the erase detection logic 708, results of the analysis are placed into the vector register 710. For example, the erase detector output 604 could be routed from the erase detection logic 708 to the vector register 710. The output of the vector register 710 indicates the erase state of each of the pages. For example, the vector register 710 could have one bit for each page, and the bit could be set or cleared according to the state of erasure of the page. In some embodiments, the vector register 710 could store information, such as address information, about a range of erased pages. This could include a starting address and/or an ending address of the range of erase pages, or a starting address and/or an ending address of a range of non-erased pages. The vector register 710 could store page counts of erased pages. Various coding schemes, for representing information about erased pages in individual or aggregate summary form, could be applied to information in the vector register 710, which in turn, could be accessed serially or in parallel, etc. The output of the vector register 710 could be used for the indicator 406 of FIG. 4 .

FIG. 8 depicts pages 224 in a block 802 of flash memory, with a boundary 804 between valid pages 224 (e.g., non-erased pages 224) and erased pages 224 as determined by the erase detector 402 of FIG. 4 . In this example, pages 224 have been written in order in the flash memory, up to the boundary 804. By reading pages one at a time, the erase detector 402 can determine which pages 224 are valid and which pages 224 are erased and detect the boundary 804. More specifically, the erase detector 402 can detect the address of the last valid flash page 224 and the address of the first erased page 224, thereby detecting the boundary 804. In some embodiments, this boundary 804 information (e.g., an address) is stored in the vector register 710 of FIG. 7B and is output from the erase detector 402 via the indicator 406 (see FIG. 4 ). In some embodiments, the storage unit 152 has an address register that holds the address of the boundary 804, i.e., holds information regarding the boundary 804. For example, the address register could hold the address of the last valid flash page 224 or the address of the first erased page 224. This is an alternative embodiment to the vector register 710 (see FIG. 7B), and is another type of erase detector output 604 (see FIG. 6 ).

FIG. 9 is a flow diagram of a method for erasure detection in a storage cluster, which can be practiced by embodiments shown in FIGS. 1-8 . Particularly, the method can be practiced by a storage unit, more specifically by an erase detector in a storage unit. In an action 902, the storage unit is powered up. The storage unit can detect that it is being powered up, and perform subsequent operations responsive to detecting the unit is being powered up. In an action 904, a connection of the storage unit to one or more storage nodes is established via a network. In some embodiments, the storage unit establishes the connection responsive to being powered up. In an action 906, reads of pages of storage memory are cycled through. This could be performed by reading successive pages of the storage memory at an interface to the storage memory. A state machine, hardware logic, or a processor could perform the cycling. In an action 908, for each page, it is determined whether the page is erased. This determination could be performed by erase detection logic such as through the utilization of logic gates, such as AND logic, valid codeword logic or a counter and threshold value, where the threshold value may be programmable as described in FIGS. 7A-7B, coupled via an interface to the storage memory. In an action 910, erasure state of each page is indicated from the storage unit to a storage node. The indication could be in the form of bits, a vector, or an address or other indication of a boundary between valid pages and erased pages, etc. Access to such an indication could be in serial or parallel, full time or upon request. In an action 912, for each erased page, error correction code operations are bypassed. The bypass could occur through software or hardware, as appropriate to the implementation.

It should be appreciated that the methods described herein may be performed with a digital processing system, such as a conventional, general-purpose computer system. Special purpose computers, which are designed or programmed to perform only one function may be used in the alternative. FIG. 10 is an illustration showing an exemplary computing device which may implement the embodiments described herein. The computing device of FIG. 10 may be used to perform embodiments of the functionality for the storage units, storage nodes or storage cluster in accordance with some embodiments. The computing device includes a central processing unit (CPU) 1001, which is coupled through a bus 1005 to a memory 1003, and mass storage device 1007. Mass storage device 1007 represents a persistent data storage device such as a floppy disc drive or a fixed disc drive, which may be local or remote in some embodiments. Memory 1003 may include read only memory, random access memory, etc. Applications resident on the computing device may be stored on or accessed via a computer readable medium such as memory 1003 or mass storage device 1007 in some embodiments. Applications may also be in the form of modulated electronic signals modulated accessed via a network modem or other network interface of the computing device. It should be appreciated that CPU 1001 may be embodied in a general-purpose processor, a special purpose processor, or a specially programmed logic device in some embodiments.

Display 1011 is in communication with CPU 1001, memory 1003, and mass storage device 1007, through bus 1005. Display 1011 is configured to display any visualization tools or reports associated with the system described herein. Input/output device 1009 is coupled to bus 1005 in order to communicate information in command selections to CPU 1001. It should be appreciated that data to and from external devices may be communicated through the input/output device 1009. CPU 1001 can be defined to execute the functionality described herein to enable the functionality described with reference to FIGS. 1-9 . The code embodying this functionality may be stored within memory 1003 or mass storage device 1007 for execution by a processor such as CPU 1001 in some embodiments. The operating system on the computing device may be MS DOS™, MS-WINDOWS™, OS/2™, UNIX™, LINUX™, or other known operating systems. It should be appreciated that the embodiments described herein may be integrated with virtualized computing system also.

Detailed illustrative embodiments are disclosed herein. However, specific functional details disclosed herein are merely representative for purposes of describing embodiments. Embodiments may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

It should be understood that although the terms first, second, etc. may be used herein to describe various steps or calculations, these steps or calculations should not be limited by these terms. These terms are only used to distinguish one step or calculation from another. For example, a first calculation could be termed a second calculation, and, similarly, a second step could be termed a first step, without departing from the scope of this disclosure. As used herein, the term “and/or” and the “/” symbol includes any and all combinations of one or more of the associated listed items.

As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes”, and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Therefore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

With the above embodiments in mind, it should be understood that the embodiments might employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to a device or an apparatus for performing these operations. The apparatus can be specially constructed for the required purpose, or the apparatus can be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.

A module, an application, a layer, an agent or other method-operable entity could be implemented as hardware, firmware, or a processor executing software, or combinations thereof. It should be appreciated that, where a software-based embodiment is disclosed herein, the software can be embodied in a physical machine such as a controller. For example, a controller could include a first module and a second module. A controller could be configured to perform various actions, e.g., of a method, an application, a layer or an agent.

The embodiments can also be embodied as computer readable code on a non-transitory computer readable medium. The computer readable medium is any data storage device that can store data, which can be thereafter read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network coupled computer system so that the computer readable code is stored and executed in a distributed fashion. Embodiments described herein may be practiced with various computer system configurations including hand-held devices, tablets, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a wire-based or wireless network.

Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or the described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing.

In various embodiments, one or more portions of the methods and mechanisms described herein may form part of a cloud-computing environment. In such embodiments, resources may be provided over the Internet as services according to one or more various models. Such models may include Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and Software as a Service (SaaS). In IaaS, computer infrastructure is delivered as a service. In such a case, the computing equipment is generally owned and operated by the service provider. In the PaaS model, software tools and underlying equipment used by developers to develop software solutions may be provided as a service and hosted by the service provider. SaaS typically includes a service provider licensing software as a service on demand. The service provider may host the software, or may deploy the software to a customer for a given period of time. Numerous combinations of the above models are possible and are contemplated.

Various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, the phrase “configured to” is used to connote structure by indicating that the units/circuits/components include structure (e.g., circuitry) that performs the task or tasks during operation. As such, the unit/circuit/component can be said to be configured to perform the task even when the specified unit/circuit/component is not currently operational (e.g., is not on). The units/circuits/components used with the “configured to” language include hardware—for example, circuits, memory storing program instructions executable to implement the operation, etc. Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. 112, sixth paragraph, for that unit/circuit/component. Additionally, “configured to” can include generic structure (e.g., generic circuitry) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.

The foregoing description, for the purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the embodiments and its practical applications, to thereby enable others skilled in the art to best utilize the embodiments and various modifications as may be suited to the particular use contemplated. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims. 

What is claimed is:
 1. A storage cluster with erasure detection, comprising: a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of user data; a plurality of storage devices, each of the plurality of storage devices having memory, each of the plurality of storage devices configured to store user data; and each of the plurality of storage devices configured to establish a connection to at least one of the plurality of storage nodes, at least one of the plurality of storage devices configured to detect if there is an erased page in the memory, and to bypass error correction of the erased page responsive to the erased page being identified.
 2. The storage cluster of claim 1 further comprising: the at least one of the plurality of storage devices configured to cycle through reads of pages in the memory of the storage device.
 3. The storage cluster of claim 1, wherein the at least one of the plurality of storage devices is configured to output information regarding a boundary between erased pages and non-erased pages.
 4. The storage cluster of claim 1, wherein the erased page is identified through one of a vector register or an address register.
 5. The storage cluster of claim 1, comprising: a register in each of the plurality of storage nodes that indicates erase state of each page of the memory based on output of an erase detection logic.
 6. The storage cluster of claim 1, further comprising: a control module that cycles reads of an interface to read each page of a block of the memory and wherein each of the plurality of storage devices includes an output indicating erase state of pages of the block of the memory.
 7. The storage cluster of claim 1, comprising: the at least one of the plurality of storage devices having hardware logic to detect the erased page in the storage memory.
 8. A method, comprising: establishing a connection between a storage device and one of a plurality of storage nodes of a storage cluster; determining, for at least one page in memory of the storage device, that the at least one page is erased; and bypassing error correction of the at least one page, responsive to determining that the at least one page is erased.
 9. The method of claim 8, wherein the determining comprises: cycling through reads of pages in the memory of the storage device.
 10. The method of claim 8, further comprising: performing a search through pages of a block of the memory to determine a boundary between erased pages and pages written in order in the block, the search including repetitions of the determining as performed by the storage device for corresponding pages in the search.
 11. The method of claim 8, further comprising: performing an error correction code operation on raw page data to produce a status indication relating to the raw page data, wherein the performing the error correction code operation is downstream of where erase detection logic of the storage device accesses the raw page data.
 12. The method of claim 8, wherein the determining includes performing a logic operation on the at least one page.
 13. The method of claim 8, further comprising: communicating from the storage device to the one of the plurality of storage nodes information regarding a boundary that separates erased pages from written pages in the memory of the storage device.
 14. The method of claim 8, wherein the determining comprises: counting bits of the at least one page to a programmable threshold value.
 15. A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising: establishing a connection between a storage device and one of a plurality of storage nodes of a storage cluster; determining, for at least one page in memory of the storage device, that the at least one page is erased; and bypassing error correction of the at least one page, responsive to determining that the at least one page is erased.
 16. The computer readable media of claim 15, wherein the method comprises: cycling through reads of pages in the memory of the storage device.
 17. The computer readable media of claim 15, wherein the method comprises: performing a search through pages of a block of the memory to determine a boundary between erased pages and pages written in order in the block, the search including repetitions of the determining as performed by the storage device for corresponding pages in the search.
 18. The computer readable media of claim 15, wherein the method comprises: performing an error correction code operation on raw page data to produce a status indication relating to the raw page data, wherein the performing the error correction code operation is downstream of where erase detection logic of the storage device accesses the raw page data.
 19. The computer readable media of claim 15, wherein the determining comprises: performing a logic operation on the at least one page.
 20. The computer readable media of claim 15, wherein the method comprises: communicating from the storage device to the one of the plurality of storage nodes information regarding a boundary that separates erased pages from written pages in the memory of the storage device. 